This invention relates to a digital signal regenerator which regenerates a high-bit-rate digital signal received from a transmission line, and more particularly to a regenerator having an improved timing recovery circuit that extracts a timing wave from the received signal.
Fiber optic digital transmission systems have tremendous capacity to transmit large amounts of information over a single optical fiber and provide a very high bit rate digital transmission. However, as the bit rate increases, an improved timing recovery technique is required for accurate regeneration of the transmitted digital data.
As a prior art regenerator, Robert L. Rosenberg et al. disclose a regenerator which is applicable at bit rates of 100 to 1000 Mbit/s and more in a paper entitled "Optical Fiber Repeatered Transmission Systems Utilizing SAW Filters" in IEEE Transactions on Sonics and Ultrasonics, Vol. 30, No. 3, pp. 119-126, May, 1983.
FIG. 1 is a partial reproduction of the Rosenberg et al. regenerator which receives a high bit rate data pulse stream, equalizes it with an equalizer 100, recovers a clock pulse stream with a timing recovery circuit 200, and regenerates the transmittal pulse stream with a decision circuit 300 gated by the clock pulse stream. The timing recovery circuit 200 differentiates the received data pulse stream from the equalizer 100 with a prefilter 201 having differential characteristics to provide the transition points of the pulse stream. The differentiated pulse stream undergoes full-wave rectification with a rectifier 202, and the rectified pulse stream is fed to a filter 203 (an SAW filter, for instance) which has bandpass characteristics and extracts a timing wave whose frequency is twice the transmitted data bit rate when the transmitted data pulse stream has an NRZ (Non-Return to zero) format. The timing wave is transformed into a square wave (timing clock stream) by a limit amplifier 204, and the phase of the timing clock stream is adjusted by a phase adjuster 205, and then supplied to the decision circuit 300 and other processing circuits. The decision circuit 300 comprises a simple digital circuit such as a D-type flip-flop, which samples the received data pulse stream coming from the equalizer 100 at the rise (or fall) of the pulses of the timing clock sequence from the phase adjuster 205, and regenerates the data pulse stream as a stream of well-shaped electrical data pulses having nearly constant amplitude and consistent timing of transitions. The phase adjuster performs a timing adjustment of the rise (or fall) positions of the clock pulses so that the clock pulse sequence drives the D-type flip-flop at center-positions in-time of individual received data pulses. The adjustment is requisite to control the decision errors that are otherwise caused by phase jitter contained in the received data pulse stream. These errors are generally likely to appear when the rise (or fall) positions in time of the received data pulse stream lie close to those of the clock pulses.
Assuming a bit rate of 100 Mbit/s, the phase adjustment that is necessary to shift over a period of the data pulse is just 10 nsec at maximum. However, the phase adjuster involves a degradation of several nsec in the rise (or fall) of the timing clock due to the effect of bandwidth limitation; thus, the permissible time range for sampling the received data bit stream is limited to several nano-seconds only. This time limitation leaves no margin long enough to adjust the timing of a clock to be applied to the decision circuit, resulting in decision errors. Moreover, when degraded timing pulses having a long rise or fall time drive the D-type flip-flop, the phase relation between the received data pulse stream and the clock pulse stream inconveniently varies, rendering adjustment of phase relation extremely difficult.